Vlsi. Circuit Complexity and Decoding Performance Analysis for Low-power Rsc Turbo-code and Iterative Block Decoders Design *
نویسنده
چکیده
A VLSI circuit complexity analysis for low-power decoder designs is presented. Two low-complexity adaptive decoder architectures incorporating the ~ecursive systematic codes (turbo-codes) and the block-codes are considered in this paper. The system performance degradation due to the algorithm approximations for realizing the low complexity decoders is also investigated. The decoders are implemented with 0.6-pm CMOS standard cell technology where their power dissipation and size information are obtained. Furthermore, the issues concerning the throughput and latency of the decoder architectures are discussed. This study provides insights into system design trade-ofls involving low-power VLSI decoders for portable wireless mobile communication systems.
منابع مشابه
VLSI Design, Optimization, and Implementation of Channel Decoding in Wireless Systems
Today’s mobile information society has a steady demand for everincreasing data rates and better quality-of-service in wireless systems. To meet this demand standards organizations involved with the wireless industry are increasingly relying on modern high-performance channel codes such as low-density parity-check (LDPC) and turbo codes. These forward error-correction codes achieve near-optimal ...
متن کاملDesign and Implementation of a Low Complexity VLSI Turbo-Code Decoder Architecture for Low Energy Mobile Wireless Communications
Channel coding is commonly incorporated to obtain sufficient reception quality in wireless mobile communications transceiver to counter channel degradation due to intersymbol interference, multipath dispersion, and thermal noise induced by electronic circuit devices. For low energy mobile wireless communications, it is highly desirable to incorporate a decoder which has a very low power consump...
متن کاملOn a turbo decoder design for low power dissipation
(Abstract) A new coding scheme called "turbo coding" has generated tremendous interest in channel coding of digital communication systems due to its high error correcting capability. Two key innovations in turbo coding are parallel concatenated encoding and iterative decoding. A soft-in soft-out component decoder can be implemented using the maximum a posteriori (MAP) or the maximum likelihood ...
متن کاملVLSI architectures for SISO-APP decoders
Very large scale integration (VLSI) design methodology and implementation complexities of high-speed, low-power soft-input soft-output (SISO) a posteriori probability (APP) decoders are considered. These decoders are used in iterative algorithms based on turbo codes and related concatenated codes and have shown significant advantage in error correction capability compared to conventional maximu...
متن کاملVLSI Architectures for Iterative Decoders in Magnetic Recording Channels
VLSI implementation complexities of soft-input soft-output (SISO) decoders are discussed. These decoders are used in iterative algorithms based on Turbo codes or Low Density Parity Check (LDPC) codes, and promise significant bit error performance advantage over conventionally used partial-response maximum likelihood (PRML) systems, at the expense of increased complexity. This paper analyzes the...
متن کامل